MC68HC908AZ60 Datasheet, PDF (164/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Break Module
Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 1 shows the structure of the break module.
IAB[15:8]
IAB[15:0]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BREAK
IAB[7:0]
Figure 1. Break Module Block Diagram
MC68HC908AZ60 — Rev 2.0
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Break Module
2-brk
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