MC68HC908AZ60 Datasheet, PDF (197/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

IRQ Pin
External Interrupt Module (IRQ)
IRQ Pin
A logic 0 on the IRQ/V_PP pin can latch an interrupt request into the IRQ
latch. A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE1 bit is set, the IRQ/V_PP pin is both falling-edge sensitive
and low-level sensitive. With MODE1 set, both of the following actions
must occur to clear the IRQ latch:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK1 bit in the interrupt status and control register (ISCR).
The ACK1 bit is useful in applications that poll the IRQ/V_PP pin and
require software to clear the IRQ latch. Writing to the ACK1 bit can
also prevent spurious interrupts due to noise. Setting ACK1 does
not affect subsequent transitions on the IRQ/V_PP pin. A falling
edge on IRQ/V_PP that occurs after writing to the ACK1 bit latches
another interrupt request. If the IRQ mask bit, IMASK1, is clear,
the CPU loads the program counter with the vector address at
locations $FFFA and $FFFB.
• Return of the IRQ/V_PP pin to logic 1 — As long as the IRQ/V_PP pin
is at logic 0, the IRQ latch remains set.
The vector fetch or software clear and the return of the IRQ/V_PP pin to
logic 1 can occur in any order. The interrupt request remains pending as
long as the IRQ/V_PP pin is at logic 0. A reset will clear the latch and the
MODE1 control bit, thereby clearing the interrupt even if the pin stays
low.
If the MODE1 bit is clear, the IRQ/V_PP pin is falling-edge sensitive only.
With MODE1 clear, a vector fetch or software clear immediately clears
the IRQ latch.
5-irq
MOTOROLA
External Interrupt Module (IRQ)
MC68HC908AZ60 — Rev 2.0
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