MC68HC908AZ60 Datasheet, PDF (158/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

ConÞguration Register (CONFIG-1)
Functional Description
The configuration register is a write-once register. Out of reset, the
configuration register will read the default value. Once the register is
written, further writes will have no effect until a reset occurs.
NOTE:
If the LVI module and the LVI reset signal are enabled, a reset occurs
when V_DD falls to a voltage, LVI_TRIPF, and remains at or below that level
for at least nine consecutive CPU cycles. Once an LVI reset occurs, the
MCU remains in reset until V_DD rises to a voltage, LVI_TRIPR.
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
LVISTOP R
Write:
LVIRST LVIPWR SSREC COPL STOP
Reset: 0
1
1
1
0
0
0
R = Reserved
Figure 1. Configuration Register (CONFIG-1)
Bit 0
COPD
0
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode. (See
Low-Voltage Inhibit (LVI) on page 185).
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
NOTE:
To have the LVI enabled in stop mode, the LVIPWR must be at a logic 1
and the LVISTOP bit must be at a logic 1. Take note that by enabling the
LVI in stop mode, the stop I_DD current will be higher.
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. (See
Low-Voltage Inhibit (LVI) on page 185).
1 = LVI module resets enabled
0 = LVI module resets disabled
MC68HC908AZ60 — Rev 2.0
156
Configuration Register (CONFIG-1)
2-config-1
MOTOROLA