MC68HC908AZ60 Datasheet, PDF (155/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
certain number of clock cycles, n_TRK, is required to ascertain that the
PLL is within the lock mode entry tolerance, ∆_Lock. Therefore, the
acquisition time, t_ACQ, is an integer multiple of n_ACQ/f_RDV, and the
acquisition to lock time, t_AL, is an integer multiple of n_TRK/f_RDV. Also,
since the average frequency over the entire measurement period must
be within the specified tolerance, the total time usually is longer than
t_Lock as calculated above.
In manual mode, it is usually necessary to wait considerably longer than
t_Lock before selecting the PLL clock (see Base Clock Selector Circuit on
page 137), because the factors described in Parametric Influences on
Reaction Time on page 150, may slow the lock time considerably.
MOTOROLA
Clock Generator Module (CGM)
MC68HC908AZ60 — Rev 2.0
153