MC68HC908AZ60 Datasheet, PDF (305/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Programmable Interrupt Timer (PIT)
I/O Registers
Address: $004D
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 4. PIT Counter Registers (PCNTH–PCNTL)
PIT Counter
Modulo Registers
The read/write PIT modulo registers contain the modulo value for the PIT
counter. When the PIT counter reaches the modulo value, the overflow
flag (POF) becomes set, and the PIT counter resumes counting from
$0000 at the next clock. Writing to the high byte (PMODH) inhibits the
POF bit and overflow interrupts until the low byte (PMODL) is written.
Reset sets the PIT counter modulo registers.
Address: $004E:$004F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
Write:
12
11
10
9
Bit 8
Reset: 1
1
1
1
1
1
1
1
Address: $004E:$004F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 5. PIT Counter Modulo Registers (PMODH–PMODL)
NOTE: Reset the PIT counter before writing to the PIT counter modulo registers.
9-tim
MOTOROLA
Programmable Interrupt Timer (PIT)
MC68HC908AZ60 — Rev 2.0
303