MC68HC908AZ60 Datasheet, PDF (302/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Programmable Interrupt Timer
I/O Registers
The following I/O registers control and monitor operation of the PIT:
• PIT status and control register (PSC)
• PIT counter registers (PCNTH–PCNTL)
• PIT counter modulo registers (PMODH–PMODL)
PIT Status and
Control Register
The PIT status and control register:
• Enables PIT interrupt
• Flags PIT overflows
• Stops the PIT counter
• Resets the PIT counter
• Prescales the PIT counter clock
Address: $004B
Bit 7
6
5
4
3
2
1
Read: POF
0
0
POIE PSTOP
PPS2 PPS1
Write: 0
PRST
Reset: 0
0
1
0
0
0
0
= Unimplemented
Figure 3. PIT Status and Control Register (PSC)
Bit 0
PPS0
0
POF — PIT Overflow Flag Bit
This read/write flag is set when the PIT counter resets to $0000 after
reaching the modulo value programmed in the PIT counter modulo
registers. Clear POF by reading the PIT status and control register
when POF is set and then writing a logic 0 to POF. If another PIT
overflow occurs before the clearing sequence is complete, then
writing logic 0 to POF has no effect. Therefore, a POF interrupt
request cannot be lost due to inadvertent clearing of POF. Reset
clears the POF bit. Writing a logic 1 to POF has no effect.
MC68HC908AZ60 — Rev 2.0
300
Programmable Interrupt Timer (PIT)
6-tim
MOTOROLA