MC68HC908AZ60 Datasheet, PDF (116/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

System Integration Module (SIM)
Illegal Address
Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address using
indexed addressing and PUL/PSH instructions will also generate an
illegal address reset.
Extra care should be exercised when using this emulation part for
development of code to be run in ROM AZ, AB or AS family parts
with a smaller memory size, since some legal addresses will
become illegal addresses on the smaller ROM memory map device
and may, as a result, generate unwanted resets.
Low-Voltage
Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V_DD voltage falls to the V_LVII voltage. The LVI bit in the SIM reset
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG-1 register are at logic zero. The RST
pin will be held low until the SIM counts 4096 CGMXCLK cycles after
V_DD rises above V_LVIR. Another sixty-four CGMXCLK cycles later, the
CPU is released from reset to allow the reset vector sequence to occur.
See Low-Voltage Inhibit (LVI) on page 185.
MC68HC908AZ60 — Rev 2.0
114
System Integration Module (SIM)
10-sim
MOTOROLA