MC68HC908AZ60 Datasheet, PDF (50/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

FLASH-1 Memory
BPR0 — Block Protect Register Bit 0
This bit protects the memory contents in the address range $8000 to
$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
By programming the block protect bits, a portion of the memory will be
locked so that no further erase or program operations may be
performed. Programming more than one bit at a time is redundant. If
both bit 1 and bit 2 are set, for instance, the address range $9000
through $FFFF is locked. If all bits are erased, then all of the memory is
available for erase and program. The presence of a voltage V_HI on the
IRQ pin will bypass the block protection so that all of the memory,
including the block protect register, is open for program and erase
operations.
FLASH-2 Block Protect Register
NOTE:
This block protect register controls the FLASH-2 array block protection.
However, since it is physically located in FLASH-1 array, the FLASH-1
control register must be used to program/erase this register.
The block protect register is implemented as a byte within the FLASH-1
memory. Each bit, when programmed, protects a range of addresses in
the FLASH-2 array.
Address: $FF81
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
BPR3 BPR2 BPR1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 3. FLASH-2 Block Protect Register (FLBPR2)
Bit 0
BPR0
0
MC68HC908AZ60 — Rev 2.0
48
FLASH-1 Memory
14-flash-1
MOTOROLA