MC68HC908AZ60 Datasheet, PDF (55/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

FLASH-2 Memory
FLASH Control Register
retention over the device lifetime. The following is the row architecture
for this array:
• $7F40–$7F7F (Row 509)
• $7F80–$7FBF (Row 510)
• $7FC0–$7FFF (Row 511)
NOTE:
Programming tools are available from Motorola. Contact your local
Motorola representative for more information.
A security feature prevents viewing of the FLASH contents.¹
FLASH Control Register
The FLASH-2 control register controls FLASH-2 program, erase, and
margin read operations.
Address: $FE11
Bit 7
6
5
4
3
2
1
Bit 0
Read:
FDIV1
Write:
FDIV0
BLK1
BLK0 HVEN MARGIN ERASE PGM
Reset: 0
0
0
0
0
0
0
0
Figure 1. FLASH-2 Control Register (FLCR2)
FDIV1 — Frequency Divide Control Bit
This read/write bit together with FDIV0 selects the factor by which the
charge pump clock is divided from the system clock. See FLASH
Charge Pump Frequency Control on page 55.
FDIV0 — Frequency Divide Control Bit
This read/write bit together with FDIV1 selects the factor by which the
charge pump clock is divided from the system clock. See FLASH
Charge Pump Frequency Control on page 55.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
3-flash-2
MOTOROLA
FLASH-2 Memory
MC68HC908AZ60 — Rev 2.0
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