MC68HC908AZ60 Datasheet, PDF (191/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Voltage Inhibit (LVI)
LVI Status Register
LVI Status Register
The LVI status register flags V_DD voltages below the LVI_TRIPF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the
LVI_TRIPF voltage for 32 to 40 CGMXCLK cycles. (See Table 1). Reset
clears the LVIOUT bit.
Table 1. LVIOUT Bit Indication
V_DD
At Level:
V_DD > LVI_TRIPR
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
LVI_TRIPF < V_DD < LVI_TRIPR
For Number of
CGMXCLK Cycles:
Any
< 32 CGMXCLK Cycles
Between 32 and 40
CGMXCLK Cycles
> 40 CGMXCLK Cycles
Any
LVIOUT
0
0
0 or 1
1
Previous Value
5-lvi
MOTOROLA
Low-Voltage Inhibit (LVI)
MC68HC908AZ60 — Rev 2.0
189