MC68HC908AZ60 Datasheet, PDF (154/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
PLL may become unstable. Also, always choose a capacitor with a tight
tolerance (±20% or better) and low dissipation.
Reaction Time
Calculation
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
• Correct selection of filter capacitor, C_F (see Choosing a Filter
Capacitor on page 151).
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K_acq is the K factor when the PLL is configured in acquisition mode, and
K_trk is the K factor when the PLL is configured in tracking mode. (See
Acquisition and Tracking Modes on page 133).
t_acq
=


V-f--_{R--D-D-D--V-A-}


K-----_A^8---_C^---_Q^{-}
t_al
=


V-f--_{R--D-D-D--V-A-}


K-----_T^4--_R^---_K^{-}
t_Lock = t_ACQ + t_AL
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See Manual and
Automatic PLL Bandwidth Modes on page 133). A certain number of
clock cycles, n_ACQ, is required to ascertain that the PLL is within the
tracking mode entry tolerance, ∆_TRK, before exiting acquisition mode. A
MC68HC908AZ60 — Rev 2.0
152
Clock Generator Module (CGM)
26-cgm
MOTOROLA