MC68HC908AZ60 Datasheet, PDF (192/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Voltage Inhibit (LVI)
LVI Interrupts
The LVI module does not generate interrupt requests.
Low-Power Modes
The WAIT and STOP instructions put the MCU in low
power-consumption standby modes.
Wait Mode
With the LVIPWR bit in the configuration register programmed to logic 1,
the LVI module is active after a WAIT instruction.
With the LVIRST bit in the configuration register programmed to logic 1,
the LVI module can generate a reset and bring the MCU out of wait
mode.
Stop Mode
With the LVISTOP and LVIPWR bits in the configuration register
programmed to a logic 1, the LVI module will be active after a STOP
instruction. Because CPU clocks are disabled during stop mode, the LVI
trip must bypass the digital filter to generate a reset and bring the MCU
out of stop.
With the LVIPWR bit in the configuration register programmed to logic 1
and the LVISTOP bit at a logic 0, the LVI module will be inactive after a
STOP instruction.
NOTE:
Note that the LVI feature is intended to provide the safe shutdown of the
microcontroller and thus protection of related circuitry prior to any
application V_DD voltage collapsing completely to an unsafe level. It is not
intended that users operate the microcontroller at lower than specified
operating voltage V_DD.
MC68HC908AZ60 — Rev 2.0
190
Low-Voltage Inhibit (LVI)
6-lvi
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