MC68HC908AZ60 Datasheet, PDF (54/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

FLASH-2 Memory
change, as will the block protection. The new silicon can be identified by
mask set.
NOTE:
In order that current software is compatible and also to prevent problems
if code should runaway, Flash program and erase algorithms should not
be embedded in software.
Functional Description
The FLASH-2 memory is an array of up to 29,488 bytes. An erased bit
reads as a logic 0 and a programmed bit reads as a logic 1. Program and
erase operations are facilitated through control bits in a memory mapped
register. Details for these operations appear later in this section. Memory
in the FLASH array is organized into pages within rows. There are 8
pages of memory per row with 8 bytes per page. The minimum erase
block size is a single row, 64 bytes. Programming is performed on a per
page basis; eight bytes at a time. The address ranges for the user
memory and the control register are:
• $0450–$04FF
• $0580–$05FF
• $0E00–$7FFF
• $FE11 FLASH-2 Control Register
When programming the FLASH, just enough program time must be used
to program a page. Too much program time can result in a program
disturb condition; in which case an erased bit on the row being
programmed becomes unintentionally programmed. Program disturb is
avoided by using an iterative program and margin read technique known
as the smart programming algorithm. The smart programming algorithm
is required whenever programming the FLASH (See FLASH
Program/Margin Read Operation on page 57). As well, to avoid the
program disturb issue each storage page of the row should not be
programmed more than once before it is erased. The 8 program cycle
maximum per row aligns with the architecture’s 8 pages of storage per
row. The margin read step of the smart programming algorithm is used
to insure programmed bits are programmed to sufficient margin for data
MC68HC908AZ60 — Rev 2.0
52
FLASH-2 Memory
2-flash-2
MOTOROLA