MC68HC908AZ60 Datasheet, PDF (57/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

FLASH-2 Memory
FLASH Charge Pump Frequency Control
FLASH Charge Pump Frequency Control
The internal charge pump, required for program, margin read, and erase
operations, is designed to operate most efficiently with a 2MHz clock.
The charge pump clock is derived from the bus clock. Table 1 shows
how the FDIV bits are used to select a charge pump frequency based on
the bus clock frequency. Program, margin read and erase operations
cannot be performed if the bus clock frequency is below 2 MHz.
FDIV1
0
0
1
1
Table 1. Charge Pump Clock Frequency
FDIV0
0
1
0
1
Pump Clock Frequency
Bus Frequency ÷ 1
Bus Frequency ÷ 2
Bus Frequency ÷ 2
Bus Frequency ÷ 4
Bus Clock Frequency
2 MHz ± 10%
4 MHz ± 10%
4 MHz ± 10%
8 MHz ± 10%
NOTE: FDIV0 and FDIV1 must be set to the same value in both flash arrays.
FLASH Erase Operation
Memory Characteristics on page 445 has a detailed description of the
times used in this algorithm. Use the following procedure to erase a
block of FLASH-2 memory:
1. Set the ERASE bit, the BLK0, BLK1, FDIV0, and FDIV1 bits in the
FLASH control register. See Table 2 for block sizes. See Table 1
for FDIV settings.
2. Insure target portion of array is unprotected, read the block protect
register: address $FF81. See Section FLASH Block Protection
on page 60 and Section FLASH Block Protect Register on page
60 for more information.
3. Write to any FLASH address with any data within the block
address range desired.
4. Set the HVEN bit.
5. Wait for a time, t_ERASE.
5-flash-2
MOTOROLA
FLASH-2 Memory
MC68HC908AZ60 — Rev 2.0
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