MC68HC908AZ60 Datasheet, PDF (300/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Programmable Interrupt Timer
PIT Counter Prescaler
The clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PPS[2:0], in the status and control register select
the PIT clock source.
The value in the PIT counter modulo registers and the selected prescaler
output determines the frequency of the periodic interrupt. The PIT
overflow flag (POF) is set when the PIT counter value rolls over to $0000
after matching the value in the PIT counter modulo registers. The PIT
interrupt enable bit, PIE, enables PIT overflow CPU interrupt requests.
POF and PIE are in the PIT status and control register.
Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consump-
tion standby modes.
Wait Mode
The PIT remains active after the execution of a WAIT instruction. In wait
mode the PIT registers are not accessible by the CPU. Any enabled
CPU interrupt request from the PIT can bring the MCU out of wait mode.
If PIT functions are not required during wait mode, reduce power
consumption by stopping the PIT before executing the WAIT instruction.
Stop Mode
The PIT is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the PIT
counter. PIT operation resumes when the MCU exits stop mode after an
external interrupt.
MC68HC908AZ60 — Rev 2.0
298
Programmable Interrupt Timer (PIT)
4-tim
MOTOROLA