MC68HC908AZ60 Datasheet, PDF (189/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Voltage Inhibit (LVI)
Functional Description
LVISTOP, enables the LVI module during stop mode. This will ensure
when the STOP instruction is implemented, the LVI will continue to
monitor the voltage level on V_DD. LVIPWR, LVISTOP, and LVIRST are
in the configuration register (CONFIG-1). (See Configuration Register
(CONFIG-1) on page 155).
Once an LVI reset occurs, the MCU remains in reset until V_DD rises
above a voltage, LVI_TRIPR. V_DD must be above LVI_TRIPR for only one
CPU cycle to bring the MCU out of reset. (See Forced Reset Operation
on page 188). The output of the comparator controls the state of the
LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V_DD
LVIPWR
FROM CONFIG-1
CPU CLOCK
LOW V_DD
DETECTOR
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
V_DD
DIGITAL FILTER
FROM CONFIG-1
LVIRST
ANLGTRIP
Stop Mode
Filter Bypass
LVIOUT
LVISTOP
FROM CONFIG-1
Figure 1. LVI Module Block Diagram
LVI RESET
3-lvi
MOTOROLA
Low-Voltage Inhibit (LVI)
MC68HC908AZ60 — Rev 2.0
187