MC68HC908AZ60 Datasheet, PDF (426/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Analog-to-Digital Converter (ADC-15)
ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the
DDR bit is at logic 1, the value in the port data latch is read.
NOTE:
Do not use ADC channels ATD14 or ATD12 when using the
PTD6/TACLK or PTD4/TBLCK pins as the clock inputs for the 16-bit
Timers.
Voltage
Conversion
When the input voltage to the ADC equals V_REFH (see ADC
Characteristics on page 439), the ADC converts the signal to $FF (full
scale). If the input voltage equals V_SSA, the ADC converts it to $00. Input
voltages between V_REFH and V_SSA are a straight-line linear conversion.
Conversion accuracy of all other input voltages is not guaranteed.
Current injection on unused ADC pins can also cause conversion
inaccuracies.
NOTE: Input voltage should not exceed the analog supply voltages.
Conversion Time
Conversion starts after a write to the ADSCR (ADC status control
register, $0038), and requires between 16 and 17 ADC clock cycles to
complete. Conversion time in terms of the number of bus cycles is a
function of ADICLK select, CGMXCLK frequency, bus frequency, and
ADIV prescaler bits. For example, with a CGMXCLK frequency of 4
MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz,
one conversion will take between 16 and 17 µs and there will be between
128 bus cycles between each conversion. Sample rate is approximately
60 kHz.
Refer to ADC Characteristics on page 439.
Conversion Time = ¹ï£§⁶^to¹⁷^A^D^C ^Cl^oc^{k C}^y^cle^s
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
Continuous
Conversion
In the continuous conversion mode, the ADC data register will be filled
with new data after each conversion. Data from the previous conversion
will be overwritten whether that data has been read or not. Conversions
MC68HC908AZ60 — Rev 2.0
424
Analog-to-Digital Converter (ADC-15)
4-adc-15
MOTOROLA