MC68HC908AZ60 Datasheet, PDF (125/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

System Integration Module (SIM)
SIM Registers
CGMXCLK
INT/BREAK
IAB
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 16. Stop Mode Recovery from Interrupt or Break
SIM Registers
The SIM has three memory mapped registers.
SIM Break Status
Register
The SIM break status register contains a flag to indicate that a break
caused an exit from stop or wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BW
R
R
R
R
R
R
R
Write:
See Note
Reset:
0
R
= Reserved
NOTE: Writing a logic 0 clears BW
Figure 17. SIM Break Status Register (SBSR)
BW — SIM Break Wait
This status bit is useful in applications requiring a return to wait mode
after exiting from a break interrupt. Clear BW by writing a logic 0 to it.
Reset clears BW.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
19-sim
MOTOROLA
System Integration Module (SIM)
MC68HC908AZ60 — Rev 2.0
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