MC68HC908AZ60 Datasheet, PDF (159/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Configuration Register (CONFIG-1)
Functional Description
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. (See Low-Voltage Inhibit (LVI) on
page 185).
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. (See
Stop Mode on page 122).
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE: If using an external crystal oscillator, do not set the SSREC bit.
COPL — COP Long Timeout
COPL enables the shorter COP timeout period. (See
Computer Operating Properly Module (COP) on page 179).
1 = COP timeout period is 2¹³ – 2⁴ CGMXCLK cycles
0 = COP timeout period is 2¹⁸ – 2⁴ CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See
Computer Operating Properly Module (COP) on page 179).
1 = COP module disabled
0 = COP module enabled
Extra care should be exercised when using this emulation part for
development of code to be run in ROM AZ, AB or AS parts that the
options selected by setting the CONFIG-1 register match exactly
the options selected on any ROM code request submitted. The
enable/disable logic is not necessarily identical in all parts of the
AS and AZ families. If in doubt, check with your local field
applications representative.
3-config-1
MOTOROLA
Configuration Register (CONFIG-1)
MC68HC908AZ60 — Rev 2.0
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