MC68HC908AZ60 Datasheet, PDF (257/480 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Peripheral Interface Module (SPI)
Queuing Transmission Data
Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates
when the transmit data buffer is ready to accept new data. Write to the
SPI data register only when the SPTE bit is high. Figure 9 shows the
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA:CPOL = 1:0).
WRITE TO SPDR ¹
SPTE
3
2
8
5
10
SPSCK (CPHA:CPOL = 1:0)
MOSI
SPRF
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
654321
654321
654
BYTE 1
BYTE 2
BYTE 3
4
9
READ SPSCR
6
11
READ SPDR
7
12
1 CPU WRITES BYTE 1 TO SPDR, CLEARING
7 CPU READS SPDR, CLEARING SPRF BIT.
SPTE BIT.
8 CPU WRITES BYTE 3 TO SPDR, QUEUEING
2 BYTE 1 TRANSFERS FROM TRANSMIT DATA
BYTE 3 AND CLEARING SPTE BIT.
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. _{9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT}
3 CPU WRITES BYTE 2 TO SPDR, QUEUEING
REGISTER TO RECEIVE DATA REGISTER, SETTING
BYTE 2 AND CLEARING SPTE BIT.
SPRF BIT.
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT ^{10 BYTE 3 TRANSFERS FROM TRANSMIT DATA}
REGISTER TO RECEIVE DATA REGISTER, SETTING
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
SPRF BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
5 BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. ¹² CPU READS SPDR, CLEARING SPRF BIT.
6 CPU READS SPSCR WITH SPRF BIT SET.
Figure 9. SPRF/SPTE CPU Interrupt Timing
19-spi
MOTOROLA
Serial Peripheral Interface Module (SPI)
MC68HC908AZ60 — Rev 2.0
255