PIC24FJ128GA Datasheet, PDF (95/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER
Upper Byte:
U-0
R-0
R-0
R-0
U-0
R/W-x⁽¹⁾ R/W-x⁽¹⁾
—
COSC2 COSC1 COSC0
—
NOSC2 NOSC1
bit 15
R/W-x⁽¹⁾
NOSC0
bit 8
Lower Byte:
R/SO-0
U-0
CLKLOCK
—
bit 7
R-0⁽²⁾
LOCK
U-0
R/CO-0
U-0
R/W-0
R/W-0
—
CF
—
SOSCEN OSWEN
bit 0
bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC2:COSC0: Current Oscillator Selection bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC2:NOSC0: New Oscillator Selection bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7
CLKLOCK: Clock Selection Lock Enabled bit
If FSCM is enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is disabled (FCKSM1 = 0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6
Unimplemented: Read as ‘0’
bit 5
LOCK: PLL Lock Status bit
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4
Unimplemented: Read as ‘0’
bit 3
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2
Unimplemented: Read as ‘0’
bit 1
SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enable secondary oscillator
0 = Disable secondary oscillator
bit 0
OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits
0 = Oscillator switch is complete
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.
2: Also resets to ‘0’ during any valid clock switch, or whenever a non-PLL Clock mode is selected.
Legend:
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
W = Writable bit
CO = Clear-Only bit
‘1’ = Bit is set
‘0’ = Bit is cleared
SO = Set-Only bit
x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 93