PIC24FJ128GA Datasheet, PDF (142/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 17-1: PMCON: PARALLEL PORT CONTROL REGISTER
Upper Byte:
R/W-0
U-0
PMPEN
—
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN
R/W-0
PTRDEN
bit 8
Lower Byte:
R/W-0
R/W-0
CSF1
CSF0
bit 7
R/W-0⁽¹⁾
ALP
R/W-0⁽¹⁾
CS2P
R/W-0⁽¹⁾
CS1P
R/W-0
BEP
R/W-0
WRSP
R/W-0
RDSP
bit 0
bit 15
PMPEN: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 14 Unimplemented: Read as ‘0’
bit 13
PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-11 ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>
00 = Address and data appear on separate pins
bit 10
PTBEEN: Byte Enable Port Enable bit (16-bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
bit 9
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
bit 8
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
bit 7-6
bit 5
CSF1:CSF0: Chip Select Function bits
11 = Reserved
10 = PMCS1 and PMCS2 function as chip select
01 = PMCS2 functions as chip select, PMCS1 functions as address bit 14
00 = PMCS1 and PMCS2 function as address bits 15 and 14
ALP: Address Latch Polarity bit⁽¹⁾
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
Note 1: These bits have no effect when their corresponding pins are used as address lines.
Legend:
R = Readable bit
-n = Value at Reset
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = bit is unknown
DS39747C-page 140
Preliminary
© 2006 Microchip Technology Inc.