PIC24FJ128GA Datasheet, PDF (130/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER
Upper Byte:
R-0 HSC R-0 HSC
U-0
U-0
U-0
R/C-0 HS
ACKSTAT TRSTAT
—
—
—
BCL
bit 15
R-0 HSC
GCSTAT
R-0 HSC
ADD10
bit 8
Lower Byte:
R/C-0 HS R/C-0 HS
IWCOL I2COV
bit 7
R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC
D/A
P
S
R/W
R-0 HSC
RBF
R-0 HSC
TBF
bit 0
bit 15
ACKSTAT: Acknowledge Status bit
(When operating as I²C master. Applicable to master transmit operation.)
1 = NACK received from slave
0 = ACK received from slave
Hardware set or clear at end of slave Acknowledge.
bit 14
TRSTAT: Transmit Status bit
(When operating as I²C master. Applicable to master transmit operation.)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission.
Hardware clear at end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
bit 9
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address.
Hardware clear at Stop detection.
bit 8
ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address.
Hardware clear at Stop detection.
bit 7
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I²C module is busy
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CRSR to I2CxRCV (cleared by software).
.
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
C = Clearable bit
HS = Set in Hardware HSC = Hardware Set/Cleared
-n = Value at POR ‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
DS39747C-page 128
Preliminary
© 2006 Microchip Technology Inc.