PIC24FJ128GA Datasheet, PDF (187/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
23.2 On-Chip Voltage Regulator
All of the PIC24FJ128GA family devices power their
core digital logic at a nominal 2.5V. This may create an
issue for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ128GA family incor-
porate an on-chip regulator that allows the device to
run its core logic from VDD.
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn, pro-
vides power to the core from the other VDD pins. When
the regulator is enabled, a low ESR capacitor (such as
tantalum) must be connected to the VDDCORE/VCAP pin
(Figure 23-1). This helps to maintain the stability of the
regulator. The recommended value for the filer capacitor
is provided in Section 26.1 “DC Characteristics”.
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic at a nomi-
nal 2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 23-1 for possible
configurations.
23.2.1 ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approxi-
mately 20 μs for it to generate output. During this time,
designated as TSTARTUP, code execution is disabled.
TSTARTUP is applied every time the device resumes
operation after any power-down, including Sleep mode.
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of 64 ms nominal delay at device start-up.
23.2.2 ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled,
PIC24FJ128GA family devices also have a simple
brown-out capability. If the voltage supplied to the reg-
ulator is inadequate to maintain a regulated level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit
(RCON<0>). The brown-out voltage levels are specific
in Section 26.1 “DC Characteristics”.
23.2.3 POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
FIGURE 23-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to VDD):
3.3V
PIC24FJ128GA
VDD
ENVREG
CEFC
(10 μF typ)
VDDCORE/VCAP
VSS
Regulator Disabled (ENVREG tied to ground):
2.5V⁽¹⁾
3.3V⁽¹⁾
PIC24FJ128GA
VDD
ENVREG
VDDCORE/VCAP
VSS
Regulator Disabled (VDD tied to VDDCORE):
2.5V⁽¹⁾
PIC24FJ128GA
VDD
ENVREG
VDDCORE/VCAP
VSS
Note 1:
These are typical operating voltages. Refer
to Section 26.1 “DC Characteristics” for
the full operating ranges of VDD and
VDDCORE.
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 185