PIC24FJ128GA Datasheet, PDF (153/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
18.1.2 RTCC CONTROL REGISTERS
REGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER⁽¹⁾
Upper Byte:
R/W-0
U-0
RTCEN⁽²⁾
—
bit 15
R/W-0
R-0
R-0
RTCWREN RTCSYNC HALFSEC
R/W-0
RTCOE
R/W-0
R/W-0
RTCPTR1 RTCPTR0
bit 8
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
Lower Byte:
R/W-0
R/W-0
CAL7
CAL6
bit 7
R/W-0
CAL5
R/W-0
CAL4
R/W-0
CAL3
R/W-0
CAL2
R/W-0
CAL1
R/W-0
CAL0
bit 0
RTCEN: RTCC Enable bit⁽²⁾
1 = RTCC module is enabled
0 = RTCC module is disabled
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the data can
be assumed to be valid.
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
HALFSEC: Half-Second Status bit
1 = Second half period of a second
0 = First half period of a second
Note: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.
RTCOE: RTCC Output Enable bit
1 = RTCC output enabled
0 = RTCC output disabled
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 151