PIC24FJ128GA Datasheet, PDF (29/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
3.2 Data Address Space
The PIC24 core has a separate 16-bit wide data mem-
ory space, addressable as a single linear range. The
data space is accessed using two Address Generation
Units (AGUs), one each for read and write operations.
The data space memory map is shown in Figure 3-3.
All Effective Addresses (EAs) in the data memory
space are 16 bits wide, and point to bytes within the
data space. This gives a data space address range of
64 Kbytes, or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space Visi-
bility area (see Section 3.3.3 “Reading Data from
Program Memory Using Program Space Visibility”).
PIC24FJ128GA family devices implement a total of
8 Kbytes of data memory. Should an EA point to a loca-
tion outside of this area, an all zero word or byte will be
returned.
3.2.1 DATA SPACE WIDTH
The data memory space is organized in byte address-
able, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.
FIGURE 3-3:
DATA SPACE MEMORY MAP FOR PIC24FJ128GA FAMILY DEVICES
MSB
Address
0001h
07FFh
0801h
Implemented
Data RAM
1FFFh
2001h
27FFh
2801h
7FFFh
8001h
MSB
LSB
SFR Space
Data RAM
Unimplemented
Read as ‘0’
LSB
Address
0000h
07FEh
0800h
SFR
Space
Near
Data Space
1FFEh
2000h
07FEh
0800h
7FFFh
8000h
Program Space
Visibility Area
FFFFh
Note: Data memory areas are not shown to scale.
FFFEh
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 27