PIC24FJ128GA Datasheet, PDF (63/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 6-1: SR: STATUS REGISTER (IN CPU)
Upper Byte:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
DC
bit 15
bit 8
Lower Byte:
R/W-0
R/W-0
R/W-0
R-0
IPL2^(1,2) IPL1^(1,2) IPL0^(1,2)
RA
bit 7
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
bit 7-5
.
IPL2:IPL0: CPU Interrupt Priority Level Status bits^(1,2)
111 = CPU interrupt priority level is 7 (15). User interrupts disabled.
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
Note 1: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority
level. The value in parentheses indicates the IPL if IPL3 = 1.
2: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 6-2: CORCON: CORE CONTROL REGISTER
Upper Byte:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
Lower Byte:
U-0
U-0
U-0
U-0
R/C-0
R/W-0
U-0
U-0
—
—
—
—
IPL3⁽¹⁾
PSV
—
—
bit 7
bit 0
bit 3
.
IPL3: CPU Interrupt Priority Level Status bit⁽¹⁾
1 = CPU interrupt priority level is greater than 7; peripheral interrupts are disabled
0 = CPU interrupt priority level is 7 or less
Note 1: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority
level.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 61