PIC24FJ128GA Datasheet, PDF (136/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 16-1: UxMODE: UARTx MODE REGISTER
Upper Byte:
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
UARTEN
—
USIDL
IREN RTSMD
—
bit 15
R/W-0⁽¹⁾
UEN1
R/W-0⁽¹⁾
UEN0
bit 8
Lower Byte:
R/W-0 HC R/W-0
WAKE LPBACK
bit 7
R/W-0 HC
ABAUD
R/W-0
RXINV
R/W-0
BRGH
R/W-0
R/W-0
PDSEL1 PDSEL0
R/W-0
STSEL
bit 0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
UARTEN: UARTx Enable bit
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimal
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
Note: This feature is only available for the 16x BRG mode (BRGH = 0).
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
Unimplemented: Read as ‘0’
UEN1:UEN0: UARTx Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT latches
Note 1: Bit availability depends on pin availability.
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in
hardware on following rising edge
0 = No wake-up enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h); cleared
in hardware upon completion
0 = Baud rate measurement disabled or completed
RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
Legend:
R = Readable bit
-n = Value at Reset
U = Unimplemented bit, read as ‘0’
W = Writable bit
HC = Hardware Cleared
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Hardware Set
x = Bit is unknown
DS39747C-page 134
Preliminary
© 2006 Microchip Technology Inc.