PIC24FJ128GA Datasheet, PDF (118/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
To set up the SPI module for the Enhanced Buffer
Master mode of operation:
1. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSn
register.
b) Set the SPIxIE bit in the respective IECn
register.
c) Write the SPIxIP bits in the respective IPCn
register.
2. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
5. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
6. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1. Clear the SPIxBUF register.
2. If using interrupts:
• Clear the SPIxIF bit in the respective IFSn
register.
• Set the SPIxIE bit in the respective IECn
register.
• Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
8. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
FIGURE 14-1:
SCKx
SPI MODULE BLOCK DIAGRAM
SSx
SDOx
SDIx
Sync
Control
Control
Clock
Select
Edge
Shift Control
bit0
SPIxSR
Transfer
Transfer
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
FCY
Prescaler
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
8-Level FIFO Buffer
(Enhanced Modes)
SPIxBUF⁽¹⁾
Read SPIxBUF
Write SPIxBUF
16
Internal Data Bus
Note 1: In Standard modes, data is transferred directly between SPIxSR and SPIxBUF.
DS39747C-page 116
Preliminary
© 2006 Microchip Technology Inc.