PIC24FJ128GA Datasheet, PDF (131/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
Upper Byte:
R-0 HSC R-0 HSC
U-0
U-0
U-0
R/C-0 HS R-0 HSC
ACKSTAT TRSTAT
—
—
—
BCL GCSTAT
bit 15
R-0 HSC
ADD10
bit 8
Lower Byte:
R/C-0 HS R/C-0 HS
IWCOL I2COV
bit 7
R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC
D/A
P
S
R/W
R-0 HSC
RBF
R-0 HSC
TBF
bit 0
bit 5
D/A: Data/Address bit (when operating as I²C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match.
Hardware set by write to I2CxTRN or by reception of slave byte.
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 2
R/W: Read/Write bit Information (when operating as I²C slave)
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware set or clear after reception of I²C device address byte.
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV written with received byte.
Hardware clear when software reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN.
Hardware clear at completion of data transmission.
.
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
C = Clearable bit
HS = Set in Hardware HSC = Hardware Set/Cleared
-n = Value at POR ‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 129