PIC24FJ128GA Datasheet, PDF (161/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
18.3 Alarm
• Configurable from half second to one year
• Enabled using the ALRMEN bit (ALCFGRPT<7>,
Register 18-3)
• One-time alarm and repeat alarm options
available
18.3.1 CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
ALRMVALH:ALRMVALL should only take place when
ALRMEN = 0.
As shown in Figure 18-2, the interval selection of the
alarm is configured through the AMASK bits
(ALCFGRPT<13:10>). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur. The alarm can also be con-
figured to repeat based on a preconfigured interval.
The amount of times this occurs once the alarm is
enabled is stored in the lower half of the ALCFGRPT
register.
When ALCFGRPT = 00 and CHIME bit = 0
(ALCFGRPT<14>), the repeat function is disabled and
only a single alarm will occur. The alarm can be
repeated up to 255 times by loading the lower half of
the ALCFGRPT register with FFh.
After each alarm is issued, the ALCFGRPT register is
decremented by one. Once the register has reached
‘00’, the alarm will be issued one last time, after which
the ALRMEN bit will be cleared automatically and the
alarm will turn off. Indefinite repetition of the alarm can
occur if the CHIME bit = 1. Instead of the alarm being
disabled when the ALCFGRPT register reaches ‘00’, it
will roll over to FF and continue counting indefinitely
when CHIME = 1.
18.3.2 ALARM INTERRUPT
At every alarm event an interrupt is generated. In addi-
tion, an alarm pulse output is provided that operates at
half the frequency of the alarm. This output is
completely synchronous to the RTCC clock and can be
used as a trigger clock to other peripherals.
Note:
Changing any of the registers, other then
the RCFGCAL and ALCFGRPT registers
and the CHIME bit while the alarm is
enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
interrupt. To avoid a false alarm event, the
timer and alarm values should only be
changed while the alarm is disabled
(ALRMEN = 0). It is recommended that the
ALCFGRPT register and CHIME bit be
changed when RTCSYNC = 0.
FIGURE 18-2:
ALARM MASK SETTINGS
Alarm Mask Setting
(AMASK3:AMASK0)
0000 – Every half second
0001 – Every second
Day of
the
Week Month
Day
Hours Minutes Seconds
0010 – Every 10 seconds
s
0011 – Every minute
ss
0100 – Every 10 minutes
m
ss
0101 – Every hour
mm
ss
0110 – Every day
0111 – Every week
d
1000 – Every month
dd
1001 – Every year⁽¹⁾
mm d d
Note 1: Annually, except when configured for February 29.
hh
hh
hh
hh
mm
ss
mm
ss
mm
ss
mm
ss
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 159