PIC24FJ128GA Datasheet, PDF (127/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
15.2 Setting Baud Rate When
Operating as a Bus Master
To compute the Baud Rate Generator reload value, use
the following equation:
EQUATION 15-1:⁽¹⁾
FSCL
=
-------------------^F---^C---^Y--------------------
2 ⋅ (I2CxBRG + 1)
or
I2CxBRG
=
⎛
⎝
-₂----_â‹^F---_F-^C--_S-^Y--_C---_L--_⎠⎞
–
1
Note 1: Based on TCY = FOSC/2, Doze mode and
PLL are disabled.
15.3 Slave Address Masking
The I2CxMSK register (Register 15-3) designates
address bit positions as “don’t care” for both 7-bit and
10-bit Address modes. Setting a particular bit location
(= 1) in the I2CxMSK register causes the slave module
to respond whether the corresponding address bit
value is a ‘0’ or ‘1’. For example, when I2CxMSK is set
to ‘00100000’, the slave module will detect both
addresses ‘0000000’ and ‘00100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
TABLE 15-1: I²C™ CLOCK RATES⁽¹⁾
Required
System
FSCL
I2CxBRG Value
FCY
(Decimal)
(Hexadecimal)
100 kHz
16 MHz
79
4F
100 kHz
8 MHz
39
27
100 kHz
4 MHz
19
13
400 kHz
16 MHz
19
13
400 kHz
8 MHz
9
9
400 kHz
4 MHz
4
4
400 kHz
2 MHz
2
2
1 MHz
16 MHz
7
7
1 MHz
8 MHz
3
3
1 MHz
4 MHz
1
1
Legend: Shaded rows represent invalid reload values for a given FSCL and FCY.
Note 1: Based on TCY = FOSC/2, Doze mode and PLL are disabled.
2: This is closest value to 400 kHz for this value of FCY.
3: FCY = 2 MHz is the minimum input clock frequency to have FSCL = 1 MHz.
4: I2CxBRG cannot have a value of less than 2.
Actual
FSCL
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
333 kHz⁽²⁾
1 MHz
1 MHz⁽³⁾
1 MHz⁽⁴⁾
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 125