PIC24FJ128GA Datasheet, PDF (144/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 17-2: PMMODE: PARALLEL PORT MODE REGISTER
Upper Byte:
R-0
R/W-0
BUSY IRQM1
bit 15
R/W-0
IRQM0
R/W-0
INCM1
R/W-0
INCM0
R/W-0
R/W-0
MODE16 MODE1
R/W-0
MODE0
bit 8
Lower Byte:
R/W-0
R/W-0
WAITB1⁽¹⁾ WAITB0⁽¹⁾
bit 7
R/W-0
WAITM3
R/W-0
WAITM2
R/W-0
WAITM1
R/W-0
WAITM0
R/W-0
R/W-0
WAITE1⁽¹⁾ WAITE0⁽¹⁾
bit 0
bit 15 BUSY: Busy bit (Master mode only)
1 = Port is busy (not useful when the processor stall is active)
0 = Port is not busy
bit 14-13 IRQM1:IRQM0: Interrupt Request Mode bits
11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
10 = No interrupt generated, processor stall activated
01 = Interrupt generated at the end of the read/write cycle
00 = No interrupt generated
bit 12-11 INCM1:INCM0: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR<15,13:0> by 1 every read/write cycle
01 = Increment ADDR<15,13:0> by 1 every read/write cycle
00 = No increment or decrement of address
bit 10 MODE16: 8/16-bit Mode bit
1 = 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers
0 = 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer
bit 9-8 MODE1:MODE0: Parallel Port Mode Select bits
bit 7-6
11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10 = Master mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)
WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits⁽¹⁾
11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY
10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY
01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY
00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY
bit 5-2 WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits
bit 1-0
1111 = Wait of additional 15 TCY
...
0001 = Wait of additional 1 TCY
0000 = No additional wait cycles (operation forced into one TCY)
WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits⁽¹⁾
11 = Wait of 4 TCY
10 = Wait of 3 TCY
01 = Wait of 2 TCY
00 = Wait of 1 TCY
Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.
Legend:
R = Readable bit
-n = Value at Reset
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS39747C-page 142
Preliminary
© 2006 Microchip Technology Inc.