PIC24FJ128GA Datasheet, PDF (56/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type
Clock Source
SYSRST Delay
System Clock
Delay
FSCM
Delay
Notes
POR
EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST
—
—
1, 2, 3
ECPLL, FRCPLL
TPOR + TSTARTUP + TRST
TLOCK
TFSCM 1, 2, 3, 5, 6
XT, HS, SOSC
TPOR + TSTARTUP + TRST
TOST
TFSCM 1, 2, 3, 4, 6
XTPLL, HSPLL
TPOR + TSTARTUP + TRST TOST + TLOCK
TFSCM 1, 2, 3, 4, 5, 6
BOR
EC, FRC, FRCDIV, LPRC TSTARTUP + TRST
—
—
2, 3
ECPLL, FRCPLL
TSTARTUP + TRST
TLOCK
TFSCM 2, 3, 5, 6
XT, HS, SOSC
TSTARTUP + TRST
TOST
TFSCM 2, 3, 4, 6
XTPLL, HSPLL
TSTARTUP + TRST
TOST + TLOCK
TFSCM 2, 3, 4, 5, 6
MCLR
Any Clock
TRST
—
—
3
WDT
Any Clock
TRST
—
—
3
Software
Any clock
TRST
—
—
3
Illegal Opcode Any Clock
TRST
—
—
3
Uninitialized W Any Clock
TRST
—
—
3
Trap Conflict Any Clock
TRST
—
—
3
Note 1:
2:
3:
4:
5:
6:
TPOR = Power-on Reset delay (10 μs nominal).
TSTARTUP = TVREG (10 μs nominal) if on-chip regulator enabled or TPWRT (64 ms nominal) if on-chip
regulator disabled.
TRST = Internal state Reset time (20 μs nominal).
TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
TLOCK = PLL lock time (20 μs nominal).
TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal).
5.2.1
POR AND LONG OSCILLATOR
START-UP TIMES
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has NOT expired (if
a crystal oscillator is used).
• The PLL has not achieved a LOCK (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
5.2.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the sys-
tem clock source when SYSRST is released. If a valid
clock source is not available at this time, the device will
automatically switch to the FRC oscillator and the user
can switch to the desired crystal oscillator in the Trap
Service Routine.
DS39747C-page 54
Preliminary
© 2006 Microchip Technology Inc.