PIC24FJ128GA Datasheet, PDF (121/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 14-3: SPIxCON2: SPIx CONTROL REGISTER 2
Upper Byte:
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN SPIFSD SPIFPOL
—
—
—
—
—
bit 15
bit 8
Lower Byte:
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
bit 7
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced Buffer enabled
0 = Enhanced Buffer disabled (legacy mode)
U-0
R/W-0
R/W-0
—
SPIFE SPIBEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 119