PIC24FJ128GA Datasheet, PDF (119/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
Upper Byte:
R/W-0
U-0
R/W-0
U-0
U-0
R-0
R-0
SPIEN
—
SPISIDL
—
—
SPIBEC2 SPIBEC1
bit 15
R-0
SPIBEC0
bit 8
Lower Byte:
U-0
R/C-0
U-0
U-0
U-0
U-0
R-0
R-0
—
SPIROV
—
—
—
—
SPITBF SPIRBF
bit 7
bit 0
bit 15 SPIEN: SPIx Enable bit
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
bit 14 Unimplemented: Read as ‘0’
bit 13 SPISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 SPIBEC2:SPIBEC0: SPIx Buffer Element Count bits
Master mode:
Number of SPI transfers pending.
Slave mode:
Number of SPI transfers unread.
bit 7
Unimplemented: Read as ‘0’
bit 6
SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded. The user software has not read the previous
data in the SPIxBUF register.
0 = No overflow has occurred
bit 5-2 Unimplemented: Read as ‘0’
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit not yet started, SPIxTXB is full
0 = Transmit started, SPIxTXB is empty
In Standard Buffer mode:
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
In Enhanced Buffer mode:
Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location.
Automatically cleared in hardware when a buffer location is available for a CPU write.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty
In Standard Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
In Enhanced Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer
location.
Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.
Legend:
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
W = Writable bit
S = Settable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Clearable bit
x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 117