PIC24FJ128GA Datasheet, PDF (28/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
3.1.1
PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in word
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 3-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
3.1.2 HARD MEMORY VECTORS
All PIC24 devices reserve the addresses between
00000h and 000200h for hard coded program execu-
tion vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.
PIC24 devices also have two interrupt vector tables,
located from 000004h to 0000FFh and 000100h to
0001FFh. These vector tables allow each of the many
device interrupt sources to be handled by separate
ISRs. A more detailed discussion of the interrupt vector
tables is provided in Section 6.1 “Interrupt Vector
Table”.
3.1.3 FLASH CONFIGURATION WORDS
In PIC24FJ128GA family devices, the top two words of
on-chip program memory are reserved for configura-
tion information. On device Reset, the configuration
information is copied into the appropriate Configuration
registers. The addresses of the Flash Configuration
Word for devices in the PIC24FJ128GA family are
shown in Table 3-1. Their location in the memory map
is shown with the other memory vectors in Figure 3-1.
The Configuration Words in program memory are a
compact format. The actual Configuration bits are
mapped in several different registers in the configura-
tion memory space. Their order in the Flash Configura-
tion Words do not reflect a corresponding arrangement
in the configuration space. Additional details on the
device Configuration Words are provided in
Section 23.1 “Configuration Bits”.
TABLE 3-1:
FLASH CONFIGURATION
WORDS FOR PIC24FJ128GA
FAMILY DEVICES
Device
Program
Memory
(K words)
Configuration
Word
Addresses
PIC24FJ64GA
22
PIC24FJ96GA
32
PIC24FJ128GA
44
00ABFCh:
00ABFEh
00FFFCh:
00FFFEh
0157FCh:
0157FEh
FIGURE 3-2:
PROGRAM MEMORY ORGANIZATION
msw
Address
000001h
000003h
000005h
000007h
most significant word
least significant word
23
16
8
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
PC Address
(lsw Address)
0
000000h
000002h
000004h
000006h
DS39747C-page 26
Preliminary
© 2006 Microchip Technology Inc.