PIC24FJ128GA Datasheet, PDF (116/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
13.4 Output Compare Register
REGISTER 13-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER
Upper Byte:
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
OCSIDL
—
—
—
—
bit 15
U-0
—
bit 8
Lower Byte:
U-0
U-0
—
—
bit 7
U-0
R-0 HC R/W-0
R/W-0
R/W-0
R/W-0
—
OCFLT OCTSEL OCM2
OCM1
OCM0
bit 0
bit 15-14 Unimplemented: Read as ‘0’
bit 13
OCSIDL: Stop Output Compare x in Idle Mode Control bit
1 = Output Compare x will halt in CPU Idle mode
0 = Output Compare x will continue to operate in CPU Idle mode
bit 12-5
bit 4
bit 3
Unimplemented: Read as ‘0’
OCFLT: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
OCTSEL: Output Compare x Timer Select bit
1 = Timer3 is the clock source for Output Compare x
0 = Timer2 is the clock source for Output Compare x
Note: Refer to the device data sheet for specific time bases available to the output compare module.
bit 2-0
OCM2:OCM0: Output Compare x Mode Select bits
111 = PWM mode on OCx, Fault pin enabled
110 = PWM mode on OCx, Fault pin disabled
101 = Initialize OCx pin low, generate continuous output pulses on OCx pin
100 = Initialize OCx pin low, generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high, compare event forces OCx pin low
001 = Initialize OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
Legend:
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
W = Writable bit
HS = Set in Hardware
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Cleared in Hardware
x = Bit is unknown
DS39747C-page 114
Preliminary
© 2006 Microchip Technology Inc.