PIC24FJ128GA Datasheet, PDF (53/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
5.0 RESETS
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Pin Reset
• SWR: RESET Instruction
• WDT: Watchdog Timer Reset
• BOR: Brown-out Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
A simplified block diagram of the Reset module is
shown in Figure 5-1.
Any active source of Reset will make the SYSRST sig-
nal active. Many registers associated with the CPU and
peripherals are forced to a known Reset state. Most
registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 5-1). A POR will clear all bits except for
the BOR and POR bits (RCON<1:0>), which are set.
The user may set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software will
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
MCLR
Glitch Filter
WDT
Module
Sleep or Idle
VDD Rise
Detect
POR
VDD
SYSRST
Brown-out
Reset
BOR
Enable Voltage Regulator
Trap Conflict
Illegal Opcode
Uninitialized W Register
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 51