PIC24FJ128GA Datasheet, PDF (129/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
Upper Byte:
R/W-0
U-0
R/W-0 R/W-1 HC R/W-0
R/W-0
R/W-0
I2CEN
—
I2CSIDL SCLREL IPMIEN A10M DISSLW
bit 15
R/W-0
SMEN
bit 8
Lower Byte:
R/W-0
R/W-0
GCEN STREN
bit 7
R/W-0
ACKDT
R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC
ACKEN RCEN
PEN
RSEN
SEN
bit 0
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I²C slave)
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
bit 5
ACKDT: Acknowledge Data bit (When operating as I²C master. Applicable during master receive.)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(When operating as I²C master. Applicable during master receive.)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit
Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress
bit 3
RCEN: Receive Enable bit (when operating as I²C master)
1 = Enables Receive mode for I²C
Hardware clear at end of eighth bit of master receive data byte.
0 = Receive sequence not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I²C master)
1 = Initiate Stop condition on SDAx and SCLx pins
Hardware clear at end of master Stop sequence.
0 = Stop condition not in progress
bit 1
RSEN: Repeated Start Condition Enabled bit (when operating as I²C master)
1 = Initiate Repeated Start condition on SDAx and SCLx pins
Hardware clear at end of master Repeated Start sequence.
0 = Repeated Start condition not in progress
bit 0
SEN: Start Condition Enabled bit (when operating as I²C master)
1 = Initiate Start condition on SDA and SCL pins
Hardware clear at end of master Start sequence.
0 = Start condition not in progress
.
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit
HS = Set in Hardware
HC = Cleared in Hardware
-n = Value at POR ‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 127