PIC24FJ128GA Datasheet, PDF (57/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
5.2.2.1
FSCM Delay for Crystal and PLL
Clock Sources
When the system clock source is provided by a crystal
oscillator and/or the PLL, a small delay, TFSCM, will
automatically be inserted after the POR and PWRT
delay times. The FSCM will not begin to monitor the
system clock source until this delay expires. The FSCM
delay time is nominally 100 μs and provides additional
time for the oscillator and/or PLL to stabilize. In most
cases, the FSCM delay will prevent an oscillator failure
trap at a device Reset when the PWRT is disabled.
5.3 Special Function Register Reset
States
Most of the Special Function Registers (SFRs) associ-
ated with the PIC24 CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed val-
ues of the oscillator Configuration bits in the FOSC
Device Configuration register (see Table 5-2). The
RCFGCAL and EECON1 registers are only affected by
a POR.
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 55