PIC24FJ128GA Datasheet, PDF (102/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
9.1.1 OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually con-
figured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired digi-
tal-only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
9.2 Configuring Analog Port Pins
The use of the AD1PCFG and TRIS registers control
the operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
9.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
9.3 Input Change Notification
The input change notification function of the I/O ports
allows the PIC24FJ128GA family of devices to gener-
ate interrupt requests to the processor in response to a
change-of-state on selected input pins. This feature is
capable of detecting input change-of-states even in
Sleep mode, when the clocks are disabled. Depending
on the device pin count, there are up to 22 external sig-
nals (CN0 through CN21) that may be selected
(enabled) for generating an interrupt request on a
change-of-state.
There are four control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin, and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
and CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
Note:
Pull-ups on change notification pins
should always be disabled whenever the
port pin is configured as a digital output.
EXAMPLE 9-1: PORT WRITE/READ EXAMPLE
MOV
MOV
NOP
btss
0xFF00, W0
W0, TRISBB
PORTB, #13
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
DS39747C-page 100
Preliminary
© 2006 Microchip Technology Inc.