PIC24FJ128GA Datasheet, PDF (138/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
Upper Byte:
R/W-0
R/W-0
R/W-0
U-0 R/W-0 HC R/W-0
R-0
UTXISEL1 UTXINV⁽¹⁾ UTXISEL0
—
UTXBRK UTXEN UTXBF
bit 15
R-1
TRMT
bit 8
Lower Byte:
R/W-0
R/W-0
URXISEL1 URXISEL0
bit 7
R/W-0
ADDEN
R-1
RIDLE
R-0
PERR
R-0
FERR
R/C-0
OERR
R-0
URXDA
bit 0
bit 15,13 UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register and as a result, the transmit
buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
bit 14 UTXINV: IrDA Encoder Transmit Polarity Inversion bit⁽¹⁾
1 = IrDA encoded UxTX idle state is ‘1’
0 = IrDA encoded UxTX idle state is ‘0’
Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit enabled, UxTX pin controlled by UARTx
0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by PORT.
UTXBF: Transmit Buffer Full Status bit (Read-Only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (Read-Only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits
11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer.
Receive buffer has one or more characters.
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
0 = Address Detect mode disabled
Legend:
R = Readable bit
-n = Value at Reset
U = Unimplemented bit, read as ‘0’
W = Writable bit
HS = Hardware Set
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Hardware Cleared
x = Bit is unknown
DS39747C-page 136
Preliminary
© 2006 Microchip Technology Inc.