PIC24FJ128GA Datasheet, PDF (139/232 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA FAMILY
REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
Upper Byte:
R/W-0
R/W-0
R/W-0
U-0 R/W-0 HC R/W-0
R-0
R-1
UTXISEL1 UTXINV⁽¹⁾ UTXISEL0
—
UTXBRK UTXEN UTXBF TRMT
bit 15
bit 8
Lower Byte:
R/W-0
R/W-0
URXISEL1 URXISEL0
bit 7
R/W-0
ADDEN
R-1
RIDLE
R-0
PERR
R-0
FERR
R/C-0
OERR
R-0
URXDA
bit 0
bit 4
RIDLE: Receiver Idle bit (Read-Only)
1 = Receiver is Idle
0 = Receiver is active
bit 3
PERR: Parity Error Status bit (Read-Only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (Read-Only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (Read/Clear-Only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1 → 0 transition) will reset the
receiver buffer and the RSR to the empty state)
bit 0
URXDA: Receive Buffer Data Available bit (Read-Only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Legend:
R = Readable bit
-n = Value at Reset
U = Unimplemented bit, read as ‘0’
W = Writable bit
HS = Hardware Set
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Hardware Cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
Preliminary
DS39747C-page 137