82375EB Datasheet, PDF (99/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
During flushing strong ordering is preserved at the Dword level (i e the Dwords are flushed to PCI memory in
the same order that they were written into the Line Buffer) Note however that strong ordering is not pre-
served at the byte or word levels (i e even if byte or word transfers were used by the EISA ISA master or
DMA to sequentially write to a Dword within a Line Buffer all of the bytes in the resulting Dword boundary are
simultaneously flushed to PCI memory)
Because strong ordering is not preserved within a Dword boundary care should be used when accessing
memory-mapped I O devices If the order of byte or word writes to a memory-mapped I O device needs to be
preserved buffered accesses should not be used By locating memory-mapped I O devices in the four pro-
grammable EISA-to-PCI memory regions buffering to these devices can be selectively disabled
6 1 2 READ STATE
If a Line Buffer contains valid read data it is in a read state Read data is placed in the Line Buffer by two
PCEB mechanisms - fetching and prefetching Data is placed in the Line Buffer on demand (fetching) when the
data is requested by a read operation from the EISA ISA master or DMA The PCEB also prefetches data that
has not been explicitly requested but is anticipated to be requested Once in the Line Buffer data is either read
by the EISA ISA master or DMA (and then invalidated) or invalidated without being read Read data is invali-
dated when
 data in the Line Buffer is read (transferred to the EISA ISA master or DMA) This prevents reading of the
same data more than once
 a subsequent read is a line miss (not to the previously accessed Line Buffer) Valid data in the current Line
Buffer is invalidated If a new line had been prefetched during access to the current line data in the
prefetched line is not invalidated unless the access also misses this line In this case the data in the
prefetched line is invalidated
 a subsequent cycle is a write Data in all Line Buffers are invalidated
If the requested data is in the Line Buffer a line hit occurs and the PCEB transfers the data to the EISA ISA
master or DMA (and invalidates the hit data in the buffer) If EISA Bus reads hit two consecutive line address-
es the PCEB prefetches the next sequential line of data from PCI memory (using a PCI Bus burst transfer)
This prefetch occurs concurrently with EISA Bus reads of data in the already fetched Line Buffer If consecu-
tive addresses are not accessed the PCEB does not prefetch the next line
A line miss occurs if the requested data is not in the Line Buffer If a line miss occurs the PCEB invalidates
data in the missed Line Buffer If the requested data is in a prefetched line the read is serviced If a line was
not prefetched or the read missed the prefetched line the PCEB invalidates any prefetched data and fetches
the Dword containing the requested data During this fetch the PCEB holds off the EISA ISA master or DMA
with wait states (by negating EXRDY) When the requested data is in the Line Buffer it is transferred to the
EISA Bus Simultaneously with the EISA Bus transfer the PCEB prefetches the rest of the line data (Dwords
whose addresses are within the line and above the Dword address of the requested data) The Dword contain-
ing the requested data and the rest of the Dwords in the line (located at higher addresses) are fetched from
PCI memory using a burst transfer unless the requested data is in the last Dword of a line In this case a
single cycle read occurs on the PCI Bus
For purposes of data read operations all four 4-Dword buffers are used to form two 8-Dword lines (32 bytes
each) There are only tow address pointers one for each line Fetching fractions of a line is accomplished as
described above (i e starting from the first requested Dword)
The MSBURST input signal is used to supplement control of the prefetch sequence The MSBURST signal
is activated only when an EISA master desires to do burst transfers to access sequential data (although this is
not an absolute EISA rule i e theoretically the data can be non-sequential after an EISA slave indicates its
ability via SLBURST ) This will occur during the first data transfer
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