82375EB Datasheet, PDF (35/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Bit
Description
7 Bank 3 Rotate Control 1^eEnable 0^eDisable
6 Bank 2 Rotate Control 1^eEnable 0^eDisable
5 Bank 1 Rotate Control 1^eEnable 0^eDisable
4 Bank 0 Rotate Control 1^eEnable 0^eDisable
3 2 Bank 2 Fixed Priority Mode Select b a
ba
00^eBank0 ^l Bank3 ^l Bank1
10^eBank3 ^l Bank1 ^l Bank0
01^eBank1 ^l Bank0 ^l Bank3
11^eReserved
1 Bank 1 Fixed Priority Mode Select 1^eREQ3 ^l CPUREQ 0^eCPUREQ ^l REQ3
0 Bank 0 Fixed Priority Mode Select 1^eREQ0 ^l PCEBREQ 0^ePCEBREQ ^l REQ0
that PCEBREQ is a PCEB internal signal
Note
3 1 10 ARBPRIX PCI ARBITER PRIORITY CONTROL EXTENSION REGISTER
Address Offset
Default Value
Attribute
Size
43h
00h
Read Write
8 bits
This register controls the fixed priority mode for bank 3 of the PCEB’s internal arbiter The ARBPRIX Register
is used in conjunction with the PCI Arbiter Priority Control (ARBPRI) Register
Bit
Description
7 1 Reserved
0 Bank 3 Fixed Priority Mode Select 1^eREQ2 ^l REQ1 0^eREQ1 ^l REQ2
3 1 11 MCSCON MEMCS CONTROL REGISTER
Address Offset
Default value
Attribute
Size
44h
00h
Read Write
8 bits
The MCSCON Register provides the master enable for generating MEMCS This register also provides read
enable (RE) and write enable (WE) attributes for two main memory regions (the 512 KByte - 640 KByte region
and an upper BIOS region) PCI accesses within the enabled regions result in the generation of MEMCS
Note that the 0-512 KByte region does not have RE and WE attribute bits The 0-512 KByte region can only be
disabled with the MEMCS Master Enable bit (bit 4) Note also that when the RE and WE bits are both 0 for a
particular region the PCI master can not access the corresponding region in main memory (MEMCS is not
generated for either reads or writes)
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