82375EB Datasheet, PDF (53/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Table 2 Read Enable Write Enable Attributes For MEMCS Decoding
Memory Attribute Registers
(Register Bits are Shown in Brackets)
Attribute
Memory Segments
Comments
MCSCON 1 0
WE RE
080000 – 09FFFFh
512K to 640K
MCSCON 3 2
WE RE
0F0000 – 0FFFFFh
BIOS Area
MAR1 1 0
WE RE
0C0000 – 0C3FFFh
Add-on BIOS
MAR1 3 2
WE RE
0C4000 – 0C7FFFh
Add-on BIOS
MAR1 5 4
WE RE
0C8000 – 0CBFFFh
Add-on BIOS
MAR1 7 6
WE RE
0CC000 – 0CFFFFh
Add-on BIOS
MAR2 1 0
WE RE
0D0000 – 0D3FFFh
Add-on BIOS
MAR2 3 2
WE RE
0D4000 – 0D7FFFh
Add-on BIOS
MAR2 5 4
WE RE
0D8000 – 0DBFFFh
Add-on BIOS
MAR2 7 6
WE RE
0DC000 – 0DFFFFh
Add-on BIOS
MAR3 1 0
WE RE
0E0000 – 0E3FFFh
BIOS Extension
MAR3 3 2
WE RE
0E4000 – 0E7FFFh
BIOS Extension
MAR3 5 4
WE RE
0E8000 – 0EBFFFh
BIOS Extension
MAR3 7 6
WE RE
0EC000 – 0EFFFFh
BIOS Extension
The PCEB generates MEMCS from the decode of the PCI address MEMCS is asserted during the first
data phase as indicated in the Figure 4 MEMCS is only asserted for one PCI clock period The PCEB does
not take any other action as a result of this decode except to generate MEMCS It is the responsibility of the
device using the MEMCS signal to generate DEVSEL TRDY and any other cycle response The device
using the MEMCS will always generate DEVSEL on the next clock This fact can be used to avoid an extra
clock delay in the subtractive decoder described in the next section
290477 – 46
NOTE
Since MEMCS is point-to-point (a sideband signal) the signal meets the guaranteed setup time to clock edge 3 (and
clock edge 4) This fast generation of MEMCS prevents the penalty caused by the decoding delay
Figure 4 MEMCS Generation
53