82375EB Datasheet, PDF (103/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
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Figure 25 EISA Memory and I O Read Write Cycle (One Extended and Two Standard Cycles)
7 1 2 EISA BACK-OFF CYCLE
For mismatched cycles to an EISA ISA slave the PCEB as a master backs off the EISA Bus by floating the
START BE 3 0 and SD 31 0 signals one and half BCLKs after START has been asserted The ESC
controls the EISA Bus for the duration of the cycle This allows the ESC to perform data translation if
necessary At the end of the cycle the ESC transfers control back to the PCEB by asserting EX16 and
EX32 on the falling edge of BCLK before the rising edge of BCLK that the last CMD is negated Refer to
the ESC data sheet for further details on master back-off and the cycle transfer control operations
Figure 26 shows an example of a back-off sequence during a 32-bit EISA master to 16-bit EISA slave Dword
read and write operation The thick lines indicate the change of control between the master and the ESC
PCEB Reading From a 16-bit EISA Slave
As a 32-bit EISA master the PCEB begins by placing the address on LA 31 2 and driving M IO The 16-bit
EISA slave decodes the address and asserts EX16 The PCEB asserts START W R and BE 3 0
The ESC samples EX32 and EX16 on the rising edge of BCLK following the assertion of START and
asserts CMD At the same time the PCEB negates START and samples EX32 When EX32 is sampled
negated the PCEB floats START and BE 3 0 Note that the PCEB continues to drive a valid address on
LA 31 0
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