82375EB Datasheet, PDF (93/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
FLSHREQ
1
0
1
0
MEMREQ
1
1
0
0
Table 7 FLSHREQ and MEMREQ
Meaning
Idle
Flush buffers pointing towards the PCI Bus to avoid EISA deadlock
Flush buffers pointing towards main memory for buffer coherency in APIC
systems
GAT mode Guarantees PCI Bus immediate access to main memory
5 4 5 1 Flushing System Posted Write Buffers
Once an EISA Bus owner (EISA ISA master or the DMA) begins a cycle on the EISA Bus the cycle can not be
backed-off It can only be held in wait states via EXRDY In order to know the destination of EISA master
cycles the cycle needs to begin After the cycle is started no other device can intervene and gain ownership
of the EISA Bus until the cycle is completed and arbitration is performed A potential deadlock condition exists
when an EISA-originated cycle to the PCI Bus forces a mandatory transaction to EISA or when the PCI target
is inaccessible due to an interacting event that also requires the EISA Bus To avoid this potential deadlock all
PCI posted write buffers in the system must be disabled and flushed before an EISA ISA master or DMA can
be granted the EISA Bus The buffers must remain disabled while the EISA Bus is occupied The following
steps indicate the PCEB (and ESC) handshake for flushing the system posted write buffers
1 When an EISA ISA master DMA or refresh logic requests the EISA Bus the ESC component asserts
EISAHOLD to the PCEB
2 The PCEB completes the present cycle (and does not accept any new cycle) and gives the EISA Bus to the
ESC by floating its EISA interface and asserting EISAHLDA Before giving the bus to the ESC the PCEB
checks to see if it itself is locked as a PCI resource It can not grant the EISA Bus as long as the PCEB is
locked
At this point the PCEB’s EISA-to-PCI Line Buffers and other system buffers (Host PCI Bridge buffers) that
are pointing to PCI are not yet flushed The reason for this is that the ESC might request the bus in order to
run a refresh cycle that does not require buffer flushing That is not known until the EISA arbitration is frozen
(after EISAHLDA is asserted)
a If the ESC needs to perform a refresh cycle then it negates NMFLUSH (an ESC-to-PCEB flush control
signal) ESC drives the EISA Bus until it completes the refresh cycle and then gives the bus to the PCEB
by negating EISAHOLD
b If the ESC requested the EISA Bus on behalf of the EISA master DMA or ISA master then it asserts
NMFLUSH and tri-states the EISA Bus The PCEB asserts the FLSHREQ signal to the Host PCI
Bridge (and other bridges) to disable and flush posted write buffers
3 When the Host PCI Bridge completes its buffer disabling and flushing it asserts MEMACK to the PCEB
Other bridges in the system may also need to disable and flush their posted write buffers pointing towards
PCI This means that other devices may also generate MEMACK All of the MEMACK s need to be
‘‘wire-OR’d’’ When the PCEB receives MEMACK indicating that all posted write buffers have been
flushed it asserts NMFLUSH to the ESC and the ESC gives the bus grant to the EISA device
4 The PCEB continues to assert FLSHREQ while the EISA ISA master or DMA owns the EISA Bus While
FLSHREQ is asserted the Host PCI Bridge must keep its posted write buffers flushed
5 MEMACK should be driven inactive as soon as possible by the Host PCI Bridge and other bridges after
FLSHREQ is negated The PCEB waits until it detects MEMACK negated before it can generate another
FLSHREQ
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