82375EB Datasheet, PDF (40/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
3 1 17 MAR1 MEMCS ATTRIBUTE REGISTER 1
Address Offset
Default Value
Attribute
Size
54h
00h
Read Write
8 bits
RE Read Enable When the RE bit (bit 6 4 2 0) is set to a 1 the PCEB generates MEMCS for PCI master
DMA or EISA master memory read accesses to the corresponding segment in main memory When the RE bit
is set to a 0 the PCEB does not generate MEMCS for PCI master DMA or EISA master memory read
accesses to the corresponding segment When the RE and WE bits are both 0 (or bit 4 in the MEMCS
Control Register is set to a 0-disabled) the PCI master DMA or EISA master can not access the correspond-
ing segment in main memory
WE Write Enable When the WE bit (bit 7 5 3 1) is set to a 1 the PCEB generates MEMCS for PCI
master DMA or EISA master memory write accesses to the corresponding segment in main memory When
this bit is set to a 0 the PCEB does not generate MEMCS for PCI master DMA or EISA master memory
write accesses to the corresponding segment When the RE and WE bits are both 0 (or bit 4 in the MEMCS
Control Register is set to a 0-disabled) the PCI master DMA or EISA master can not access the correspond-
ing segment in main memory
Bit
Description
7
0CC000 – 0CFFFFh Add-on BIOS WE 1^eEnable 0^eDisable
6
0CC000 – 0CFFFFh Add-on BIOS RE 1^eEnable 0^eDisable
5
0C8000 – 0CBFFFh Add-on BIOS WE 1^eEnable 0^eDisable
4
0C8000 – 0CBFFFh Add-on BIOS RE 1^eEnable 0^eDisable
3
0C4000 – 0C7FFFh Add-on BIOS WE 1^eEnable 0^eDisable
2
0C4000 – 0C7FFFh Add-on BIOS RE 1^eEnable 0^eDisable
1
0C0000 – 0C3FFFh Add-on BIOS WE 1^eEnable 0^eDisable
0
0C0000 – 0C3FFFh Add-on BIOS RE 1^eEnable 0^eDisable
3 1 18 MAR2 MEMCS ATTRIBUTE REGISTER 2
Address Offset
Default Value
Attribute
Size
55h
00h
Read Write
8 bits
RE Read Enable When the RE bit (bit 6 4 2 0) is set to a 1 the PCEB generates MEMCS for PCI master
DMA or EISA master memory read accesses to the corresponding segment in main memory When this bit is
set to a 0 the PCEB does not generate MEMCS for PCI master DMA or EISA master memory read
accesses to the corresponding segment When the RE and WE bits are both 0 (or bit 4 in the MEMCS
Control Register is set to a 0-disabled) the PCI master DMA or EISA master can not access the correspond-
ing segment in main memory
40